HPD
Advanced Cryogenics Lab

Technical Presentations / Papers

Low-noise amplifier cryogenic testbed validation in a TaaS (Testing-as-a-Service) framework
 | Boiko, Zhang, Jorgesen, Engelmann, Grosskopf, Paske

As quantum computers based on superconducting qubit processors scale, cryogenic microwave components in the qubit control and readout chain must be appropriately tested and qualified to ensure consistent and high-fidelity quantum computation. However, the intersection of superconducting cryogenics and microwave electronics is a new domain with limited technical and commercial expertise. In this paper we validate a TaaS (testing-as-a-service) framework using an organizational workgroup model that consists of (1) a commercial Test House, (2) standard temperature Component Manufacturer, (3) Academic Partner, and (4) System Integrator to demonstrate a scalable model for the qualification of cryogenic microwave components. The goal of this model is to secure the supply chain and support the rapid growth of Quantum Computing (QC) technologies. The component test vehicle presented in this paper is a low-noise amplifier (LNA) which is a crucial component in the cryogenic chain to ensure adequate signal-to-noise of the qubit readout. We devise standard test metrics and protocols by which LNA performance is measured, including key parameters such as gain and flatness, reflection and isolation, operating bandwidth, and noise figure. We present details of the cryogenic testbed customized for LNA qualification, outline test methodologies, and present a suite of standard processes that are used to systematize data collation and reporting. The testbed is validated by reproducing parameters of a pre-characterized LNA. Its value is demonstrated by characterizing a proof-of-concept cryogenic LNA prototype. Finally, we describe the extension of our TaaS framework toward testing at scale for various active and passive cryogenic components used in QC.

Fully Automatic 4K Cryogenic Probe Station for DC and Microwave Measurements on 150mm and 200mm Wafers | West
Technical Presentation at IMS 2022

Robust maturation of cryogenic electronics has been limited by the lack of high-throughput measurement capabilities, especially for electronics that operate at 4 K. Automated on-wafer probing to characterize the dc and RF performance of components and complete circuits has been a critical element in the development of room temperature electronics. We report here the development of a fully automated wafer prober that operates with the wafer cooled to a temperature of 4 K and has the ability to null the ambient magnetic field to below 100 nT, which is important for measuring superconducting circuits with the wafer prober.

Accelerated Solid State Qubit Pre-Screening | DeGrave
Industry Workshop at IMS 2022

Until recently, quantum engineers operating devices at milli-Kelvin temperatures are faced with the difficulties and inconveniences of long development cycles The major bottlenecks include time-consuming wire bonding, expensive packaging processes prior to device cooldown, and long cooldown times for dilution refrigerators This workshop presents an integrated measurement solution for Pre-Screening qubit devices, allowing quantum engineers to eliminate wire-bonding and packaging from cryogenic test processes and to provide critical qubit performance parameters at 50 mK, thus streamlining device deployment, and reducing the time for development cycles

Strategies for Enabling Quantum Development with Test and Measurement from 77K down to milli-Kelvin | DeGrave
MicroApps Seminar at IMS 2022

Quantum computing will likely utilize numerous new technologies which operate at different cryogenic temperatures. For example, a quantum computer might deploy CMOS memory modules at 77 K, superconducting control chips at 4K, and a quantum processing unit (QPU) at less than 20 mK. To develop and deploy these various subsystems and technologies, it is vital to reliably and efficiently test and measure them at or near their operating temperatures.

Wafer-Scale Characterization of a Superconductor Integrated Circuit Fabrication Process, Using a Cryogenic Wafer Prober
IEEE Transactions on Applied Superconductivity, Vol. 32, No. 5, August2022

Using a fully automated cryogenic wafer prober, we measured superconductor fabrication process control monitors and simple integrated circuits on 200-mm wafers at 4.4 K, including SQIF-based magnetic field sensors, SQUID-based circuits for measuring inductors, Nb/Al-AlOx/Nb Josephson junctions, test structures for measuring critical current of superconducting wires and vias, resistors, etc., to demonstrate the feasibility of using the system for characterizing niobium superconducting devices and integrated circuits on a wafer scale. Data on the wafer-scale distributions of the residual magnetic field, junction tunnel resistance, energy gap, inductance of multiple Nb layers, and critical currents of interlayer vias are presented. A comparison with existing models is made. The wafers were fabricated in the SFQ5ee process, the fully planarized process with eight niobium layers and a layer of kinetic inductors, developed for superconductor electronics at MIT Lincoln Laboratory, Lexington, MA, USA. The cryogenic wafer prober was developed at HPD/FormFactor, Inc., Boulder, CO,USA.