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• Create Date January 13, 2022
• Last Updated January 13, 2022

Too Hot to Test for Leading-edge SoC and Heterogenous Integrated IC Stack

Leading-edge AI/Graphic/mobile processors, DRAM devices, and heterogeneous integrated IC stacks are all facing the same set of thermal management challenges -- DUT is too hot to test. Even at room temperature wafer chuck setting, a mobile SoC device junction temperature can get well above 100 to 150C. For DRAM full-wafer testing, 1-2K watts of power could be applied during 1-TD testing, posting challenges for test cell thermal management. This results in inaccurate test results or frequently burned probes which cause test cell downtime. As the heterogeneous integration becomes more popular, the thermal challenges to test the base-die with multi-chips stacked on top further exuberate as the thermal loading per silicon area can increase by order of magnitude. You can’t improve what you can’t measure. FormFactor latest low-thermal-resistance (LTR) wafer chuck technology applies multiple temperature sensors to accurately detect DUT temperature and adjust heat dissipation to achieve the desired test temperature. LTR has shown promising results in production test to address the too hot to test challenge.

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