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Current Carrying Capacity Maximization in Probe Cards and the Path to An Unburnable Probe

Data centers and High-Performance-Compute (HPC) applications are quickly approaching, and even exceeding, 1 kW of total power in a single chip under normal operating conditions. In addition to new applications, the transition to new nodes further increases the total power per unit area in a semiconductor, which compounds the challenge of increased power and thermal output of a device during testing, even in low-power consumption applications such as mobile application processors. This continuous increase in device output power creates several challenges regarding wafer testing, particularly in maintaining contactor integrity at high current and in high-temperature environments. To address this trend, higher CCC in the probe during testing must advance at a rate similar to the increased power observed in the DUT, leading to increased uptimes and lower cost of testing. This paper will discuss several techniques that can be utilized in the probe card to maximize CCC and achieve an effective CCC of >2.5 A in a probe card at an 80 um minimum pitch. These techniques include both new probe developments and architectural improvements to maintain probe integrity in a high-stress, high-current environment.

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