FormFactor’s CEO, Mike Slessor, will be giving the Thursday keynote speech and participating in a panel discussion at the upcoming International Test Conference (ITC 2024). We are also a Silver Sponsor for this event.

International Test Conference
San Diego, CA
Hilton San Diego Bayfront
November 3 – 8, 2024

Keynote Speech: Thursday, November 7th, 9 – 10am: From the Shadows to the Spotlight – Probe’s Role in Enabling Electronics Industry Innovation

Once seen as a straightforward test insertion, today’s probe technology has evolved into a cornerstone of cutting-edge semiconductor manufacturing. As the industry pushes the boundaries with advanced packaging architectures, like 2.5-D and 3-D chiplet stacking, probe’s role has become pivotal in enabling economically viable production at the leading edge. In this session, we’ll dive into the driving forces behind probe’s skyrocketing performance and capabilities, from testing high-bandwidth-memory DRAM to powering high-performance compute xPUs and even co-packaged electro-optical silicon photonics.

To keep pace with the growing complexity and intensity of semiconductor testing, test suppliers have developed breakthrough solutions to meet the demands of each application. Consider a state-of-the-art DRAM test cell: it tests every die on a wafer simultaneously through a probe card with over 100,000 individual probes—each as fine as a human hair—conducting high-frequency currents across extreme temperature ranges, all while adapting to the wafer’s topography. This level of performance has only been possible through radical advancements in test technologies and a rapidly evolving supplier landscape.

Looking ahead, this relentless pace of innovation shows no signs of slowing. To continue meeting the industry’s rigorous demands and enabling future breakthroughs, seamless collaboration between test suppliers and customers will be more critical than ever.

Panel Session E4: Wednesday, November 6th, 4:30 – 6pm: Chiplet Manufacturing Test

Organizers: Saman Adham – TSMC (USA) and Erik Jan Marinissen – imec (Belgium)

Panelists:

Phil Byrd – Micron (Idaho, USA)
Omer Dossani – Amkor Technology (Arizona, USA)
Darshan Kobla – Microsoft (Texas, USA)
Shu-Liang Nin – TSMC (Taiwan)
Mike Slessor – FormFactor (California, USA)
Lawrence van der Vegt – MPI Corporation (California, USA)

In recent years, chiplet-based design has emerged as a game-changing solution to the limitations of traditional monolithic ICs. By partitioning complex systems into smaller, individual chiplets—arranged side-by-side or stacked—this approach promises significant gains in performance, scalability, and cost-efficiency. However, with these advantages come new challenges, particularly in testing and manufacturing.

Interestingly, the test community has yet to coin a specific name for this new breed of chips. Is it because test engineers aren’t fully engaged with this technology, or are the testing challenges too daunting? Can we rely on traditional Design-for-Test (DfT) and Built-in Self-Test (BIST) techniques, or will they fall short? Moreover, chiplet design introduces multiple potential test stages: pre-bond, mid-bond, post-bond, and packaged tests. Do we need to test at every stage, or can the test flow be streamlined? How reusable is the DfT across these integration steps?

This special panel session brings together experts representing a broad spectrum of the industry to tackle these questions head-on. Each speaker will share their perspective in a brief 10-minute presentation, setting the stage for a lively plenary panel discussion. You, the audience, are invited to join the conversation, ask questions, and help clarify any remaining uncertainties in this fast-evolving field.

We hope to see you in San Diego!