FormFactor’s COMPASS Japan will take place in Tokyo on Wednesday, February 28th. Here’s a sneak peek at some of the presentations for the event whose theme is Megatrends in Test and Measurement. Be sure to register here.

Pharos Vertical and Edge Coupling Low Loss SiPh Wafer Test with Fully Automated Calibration – From Probe Install to Successful V-groove Wafer Level Test in 90 Minutes – Kainoa Kekahuna, Applications Engineering Manager, FormFactor

Kainoa will explore FormFactor’s leading-edge silicon photonics technology, Pharos, which excels in V groove edge coupling and achieving minimal loss in grating coupler connections. Additionally, we’ll delve into the latest enhancement of their silicon photonics software suite – a four-click automated calibration process.

FormFactor’s SiPh solution is equipped with a unique power measurement feature that precisely quantifies laser output from Pharos fiber channels. This innovation provides users with the convenience of seamlessly transitioning between direct wafer measurements and auxiliary site verification of laser power. The system’s ability to automatically align one of its eight probe channels, as well as to return to the previously measured die or subdie, is controlled through a single integrated command. This eliminates the need for manual adjustments at the auxiliary site, ensuring accuracy and saving valuable time.

Furthermore, the introduction of a four-click automated calibration process in FormFactor’s system streamlines the calibration procedure, removing the risk of manual errors. This ensures consistent, accurate calibration results every time, significantly reducing the time spent on calibration tasks.

Cryogenic Measurements of Quantum Control Chips for Large-scale Silicon Quantum Computers – Takuji Miki, Ph. D., Associate Professor, Graduate School of Science, Technology and Innovation, Kobe University

The operation of quantum control chips at cryogenic temperatures is a key requirement for the development of extensive quantum computers. Our presentation will highlight a specific design of a cryogenic analog circuit for controlling silicon spin qubits, including its evaluation at a 4 Kelvin temperature setting. We will also discuss the results from cryogenic testing of a multi-chip assembly structure designed for qubit placement, evaluated at a very low temperature of 100 milliKelvin.

Emerging Trends, Challenges, and Solutions for Probing Advanced Packaged Devices – Saeki Takao – Sr. Director, Manufacturing Engineering, FormFactor

As we transition into the era beyond Moore’s Law, the semiconductor industry is increasingly turning to advanced packaging as a key technology to drive the next wave of devices. These devices demand higher performance, more computing power, and greater frequency bandwidth, all while aiming to minimize costs. In this context, 2.5D and 3D IC packaging technologies are becoming vital for a growing range of applications, addressing these heightened performance needs. This evolution brings with it new challenges in testing, crucial for maintaining device performance and yield at a sustainable cost. Testing strategies and solutions are adapting to meet these demands.

In this presentation, we will examine the latest trends in advanced packaging, particularly focusing on 2.5D and 3D IC technologies. We’ll discuss testing requirements from the perspective of probe cards and explore probe card solutions that are being developed to cater to the testing needs of both current and future generations of devices.

The Importance of Data Integrity in Wafer Testing – Jerry Broz, Sr. VP of Business Development & Strategic Marketing, Delphon Industries

The costs associated with developing, designing, and manufacturing advanced monolithic semiconductors using cutting-edge processes now constitute a staggering 70-80% of the overall device expense. To address consumer demands for better performance, smaller size, lighter weight, and reduced power consumption, all at a lower cost, the industry is increasingly adopting IP integration strategies. These strategies leverage the strengths of various components like processors, sensors, RF, and memory modules. However, in such complex systems, a single failure can be extremely costly, raising the stakes for testing complexity and necessitating the highest standards of data quality and integrity. Integrated Device Manufacturers (IDMs) and foundries are thus placing greater emphasis on comprehensive test coverage prior to integration and advanced packaging to ensure the adequacy of semiconductor IP.

Electrical testing of wafers or devices involves physical contact, or “touchdowns,” using advanced probe cards. To address the challenges of wafer-level testing and support more proactive, or “shift left,” testing methodologies for identifying device failures cost-effectively, advancements in test-cell tooling, innovative probe cards, and new materials are essential. Effective and economical probe cleaning strategies are fundamental to maintaining data quality and achieving high first-pass yields amidst increasing test complexity.

This presentation will delve into the processes of probe card cleaning, underscoring the technical and commercial challenges that necessitate innovation, collaboration, partnerships, and an interdisciplinary approach to problem-solving. A deep understanding of materials and a collaborative spirit are crucial for developing the cleaning materials required to maintain contact reliability during advanced wafer-level testing.

There are other presentations covering quantum computing, the latest trends in chiplet integration technologies, and parametric test to be added to the agenda, so be sure to visit our COMPASS Japan website for details.