November 3, 2022
Semiconductor manufacturers are on a relentless drive to reduce the total cost of test at sort. A major contributor to reducing the cost of test is increasing simulations of the Device Under Test which requires a subsequent increase in the probe card active area.
FormFactor just finished up the SWTest Asia Conference in Taiwan. We presented four papers covering a number of topics. Here’s a summary:
Probe Card Challenges for Expanding Arrays of Fine Pad Pitch Devices to Test Under Wide Temperature Range
Pouya Dastmalchi, PhD, and Cameron Harker (Formfactor – USA)
Presented by Pouya Dastmalchi, PhD (Formfactor – USA)
Semiconductor manufacturers are on a relentless drive to reduce the total cost of test at sort. A major contributor to reducing the cost of test is increasing simulations of the Device Under Test which requires a subsequent increase in the probe card active area. For wire bond applications, increasing the active area must also meet the requirements of an extremely wide temperature range, very fine pitch and electrical performance. These factors, along with other considerations, increase the probe card design complexity exponentially.
Vertical probe card solutions must evolve to meet these new testing challenges both at an architectural and probe level. Probe card architectures need to be managed for mechanical stresses and CTE match between substrate and guide plates, support electrical performance requirements to meet device test requirements and achieve increased spring count requirements.
FormFactor has developed a new probe card architecture that meets these challenges. The recently qualified 60um pitch probe card architecture has been developed to address the challenges of fine pitch, high CCC, high temperature range for wire bond probing applications. Additionally, the new architecture incorporates the benefits of an optimized 60um capable MEMS vertical spring, optimal material selection and automated manufacturing processes which provides superior lifetime, stable CRES and tighter pin-pad alignment.
Next Generation DRAM Temperature Requirements and Impacts to Full Wafer Contactor Probe Card Performance
Myung Jin Lee (FormFactor – USA) and Hyun Ae Lee (Samsung Electronics – Korea)
Traditional DRAM devices for server, mobile and commercial applications require wafer test temp range from -25oC to 10oC for cold, up to 85oC to 105oC for hot test. Emerging new devices for automotive, industrial and military applications require increased test temp range from -40oC to 125 oC and higher. DRAM probe card solutions for volume production are based on 300mm, full wafer contact architectures to support 1TD solutions. Expansion and contraction of the 300mm wafer for these increased temperature ranges create significant challenges for full wafer contactor probe cards including CTE matching to the movement of the full 300mm wafer. In addition, requirement trends for smaller pad pitch and smaller pad sizes, increase the probing challenges to be solved. Probe card solutions not only need to satisfy the challenges of reduced pad pitch, pad size and increase temperature range but also must consider PCB component selection and strategic component placement, chuck movement time and strategies to maintain probe card thermal stability.
Known Good Die Memory Wafter Test Challenge Beyond DDR5 4GHz/8Gbps Speed
Alan Liao (FormFactor – USA)
The recent industry-wide adoption of heterogeneous integrated systems enabled by 2.5D and 3D advanced packaging technology is driving up the demand for known-good-die. Together with the advancement of DRAM and High Bandwidth Memory (HBM) native speed capability, the latest memory DDR5 and NAND flash devices are running beyond 4GHz (8Gbps) which is pushing the limit on existing ATE testers. In 2021, a joint effort between SK Hynix and FormFactor, successfully demonstrated 3GHz is achievable. In addition, Formfactor with industry tester partners has extended test solutions to beyond 4GHz on both DDR5 and NAND flash KGD wafer test.
High Parallelism Probe Card on V93K Direct-Probe™ System to Increase Testing Throughput on Automotive IC
John Kao (Formfactor – Taiwan)
A Solution to Enable High Parallelism Test on V93K Direct-Probe System, the FFI TrueScale Matrix product design provides larger active area enable more TD efficient solution. Wide range dual temp test design for automotive has better thermal planarity control, to avoid thermal gradients in probe card produce differential expansion across probe card components and produce probe card bow.
For more information, and to explore other technical papers, please visit our website.