LIVERMORE, Calif. – April 10, 2007 – FormFactor, Inc. (Nasdaq: FORM) today announced the introduction of its PH150XP wafer probe card, an extension of the company’s benchmark PH150 product family for DRAM wafer testing. The PH150XP probe card offers several yield and throughput enhancements to enable DRAM manufacturers to achieve additional reductions in their overall cost of test. PH150XP probe cards have already been shipped to leading memory manufacturers for evaluation.

The PH150XP complements FormFactor’s new Harmony XPTM wafer probe solution, which was introduced this past January. While the Harmony XP probe card is designed for full-area 300- mm wafer testing for 1GB and higher-density DRAM devices, the PH150XP is a more cost- effective solution for testing smaller-sized, smaller density DRAM devices (512MB and below) where tester resources mandate four or more touchdowns per wafer.

“With demand for cellular phones, MP3 players and other mobile handset products continuing to drive the need for consumer DRAM devices, our customers are looking to us to provide wafer probe solutions that help enable them to meet their time-to-market requirements at the lowest cost of test,” stated Igor Khandros, chief executive officer of FormFactor. “With the addition of our new PH150XP probe card to FormFactor’s advanced suite of wafer probe solutions, our customers can now optimize wafer testing for the full range of their DRAM products.”

Enabling Higher Test Yields

As mobile applications continue to drive down device operating voltages, IC manufacturers face a growing problem—noise arising from the delivery of power between the test equipment and the device. By maximizing the use of dedicated power and ground pins on the device, this noise can be reduced, thereby minimizing the potential for false test results. The PH150XP probe card features a new MicroSpring® contact design that can accommodate more than 25,000 contacts, making it an ideal solution for testing these high pin-count mobile DRAM

devices. Architectural enhancements on the PH150XP probe card also enable tighter planarity and higher positional accuracy with the wafer during probing. In addition to supporting smaller test pad geometries, these enhancements reduce excessive scrub marking, which can damage the test pads and result in yield loss. Minimizing scrub marks is especially important for known good die (KGD) and other applications that require multiple test insertions, or stages at which the device is probed.

Maximizing Test Cell Throughput and Uptime

Probing at multiple temperatures is important for determining device functionality across a range of operating conditions. However, as the wafer changes temperature it expands or contracts slightly, which may cause misalignment with the probe card that can damage the device under test and may lead to poor electrical contact and inaccurate test results. An option is available with the PH150XP probe card that allows it to compensate for these temperature variations to support dual temperature testing at very small pad sizes, while reducing soak time (the time needed to bring the probe card to the required test temperature) to enable higher probe card availability and test throughput. With this option, probe positions remain stable during probe card installation, wafer changes and probe mark inspection—ensuring controlled probing conditions, and enabling faster setup.

Forward-Looking Statements

Statements in this press release that are not strictly historical in nature are forward-looking statements within the meaning of the federal securities laws, including statements regarding the performance of our products. These forward-looking statements are based on current information and expectations that are inherently subject to change and involve a number of risks and uncertainties. Actual events or results might differ materially from those in any forward- looking statement due to various factors, including, but not limited to the company’s ability to: provide cost-effective products and solutions to meet customer needs and requirements, including their time-to-market requirements at the lowest cost of test; optimize DRAM wafer testing with its wafer test solutions; deliver to its customers wafer probe solutions that enable higher test yields, maximize test cell throughput and uptime, and enable its customers to more fully utilize the resource capabilities of their test equipment; and help its customers lower their overall cost of test. Additional information concerning factors that could cause actual events or results to differ materially from those in any forward-looking statement is contained in the company’s Form 10-K for the fiscal year ended December 30, 2006 and the company’s subsequent 10-Q and 8-K filings, which the company files with the Securities and Exchange Commission (“SEC”). Copies of the company’s SEC filings are available at http://investors.formfactor.com/edgar.cfm. The company assumes no obligation to update the information in this press release, to revise any forward-looking statements or to update the reasons actual results could differ materially from those anticipated in any forward-looking statements.