Wafer-Level Testing for AI Processors
Artificial Intelligence (AI), once confined to science fiction, now impacts daily life. From voice assistants and autonomous vehicles to healthcare diagnostics and supply chain optimization, AI is reshaping industries.
At the core of AI lies its neural network architecture, which mimics the way biological brains process information—recognizing patterns through repetition and example, as opposed to the sequential logic of traditional programming. These neural networks consist of vast arrays of interconnected nodes, each functioning like a synthetic neuron. Each node acts as an independent algorithm, exchanging data to collectively solve complex problems. To train and refine these models, immense computational power is needed to simulate the behavior of each node through countless cycles. This demand for high-performance processing makes AI an ideal candidate for cutting-edge semiconductor technologies capable of massive parallel computation.
As AI evolves, specialized hardware and testing solutions to support these parallel workloads are increasingly critical. The rapid expansion of AI applications—from autonomous driving and edge computing to high-performance computing (HPC) and 5G networks—has placed unprecedented pressure on semiconductor manufacturers to deliver chips that can perform at scale while maintaining energy efficiency and reliability.
Advanced AI Requires Advanced IC Packaging
Massive parallelism once existed exclusively in the realm of supercomputers, but recent advances in chip technology allow it to now reside on a single IC substrate that integrates literally billions of transistors. One key breakthrough in this area is the emergence of advanced packaging, which allows multiple logic functions to be positioned within very close proximity to each other to maximize speed and minimize energy consumption.
VIDEO: Solving the challenges of very high power and very high signal count with hybrid MEMS technology.
Probing the Inner Limits
Each layer must be functionally verified before going on the advanced package die stack stack, and may include up to 4000 test points called microbumps that lead to data paths, power supplies and ground. Microbump test points are positioned extremely close to each other, often within 45 μm. And each presents a very small probe target, on the order of 25 μm.
Heat issues complicate this challenge. At the wafer level, extremely large populations of test points generate substantial amounts of heat during probing operations. To prevent overloads that burn out probes and invalidate test results, heat levels must be continually monitored throughout the test cycle.
At FormFactor we’ve met this challenge with a new generation of wafer probing cards that can land successfully on arrays of microbumps as small as 25μm in diameter—smaller than a human hair. During operation, each probe can carry more than an amp of current without overheating and warping. It’s all done through our proprietary MEMS technology and carefully formulated metal alloys that resist the effects of heat and mechanical stress.
Hybrid MEMS probing technology for high bandwidth memory
Hybrid MEMS Insights: FormFactor’s CTO Jarek Kister explains how FormFactor’s Hybrid MEMS technology enables engineers to balance contact force, high current carrying capability and ultra-fine pitch to optimize for advanced wafer probe requirements.
Apollo Probe Card
| Apollo vertical probe cards are suitable for area-array and perimeter-layout probing applications, including both flip chip and pre-bump or aluminum pad application. Apollo is the industry-leading flip chip probe card of choice for graphics processors, game console microprocessors, and automotive microcontrollers. Leveraging proprietary manufacturing technology, Apollo delivers excellent reliability and quality for multi-DUT testing, and technology scalability to address a broad range of testing requirements.
• Broad range of vertical and vertical MEMS probe options, scalable to 80 um pitch • Proprietary manufacturing technology for reduced CRES and improved wafer yield • Superior current-carrying capability for enhanced production uptime and quick time-to-market • Minimum grid-array pitch of 80 μm (or Minimum grid array pitch of 135μm) • Supports high multi-site testing (X8–X16) with ultra high pin count (20 – 30k pins) • Ultra low-force vertical MEMS probe options for Cu pillar probing, 1.5 to 2.5 g/probe • Flip-chip bump or Cu pillar probing • High current carrying option, up to 1A/probe • Ultra-low force to allow high-temperature probing on solder-capped Cu pillars. <2 g/probe in production, demonstrated minimum solder cap disturbance post-probing to ensure back-end packaging reliability
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Kepler™️ Probe Card
Kepler vertical probe cards meet the challenges of large active area vertical probing. Kepler probe cards are provide thermally stable vertical spring architecture to support a wide temperature—common to automotive testing. Kepler supports tight pad pitch, multiple pad rows and core pads allowing for probing on smaLl pads with minimal pad damage. Kepler delivers stable electrical performance with a low, stable CRES.
• Utilizes multi-layer ceramic (MLC) space transformer
• Proprietary fine pitch, low force vertical 2D MEMS springs
• Full planarity/tilt adjustment capability>br>
• Flexible probe head configuration to support various device layouts, array sizes and pad pitch requirements
• Service friendly architecture—field replaceable springs and components
Active Thermal Control
We also provide solutions that continually control the temperature of the chuck, which holds the wafer in place during probing. Temperature sensors constantly monitor the interface between the chuck and wafer, with liquid cooling applied to keep heat levels within acceptable limits.
As AI continues its migration into new generations of silicon, we’re committed to being there with wafer probe solutions that help make it possible.
Active temperature control is crucial–Thermal Chuck is an integral part of the test cell
