Be sure to join us at the Semiconductor Wafer Test Conference (SWTest) on June 2-5 at the Rancho Bernardo Inn in San Diego, California. We will be presenting the following six papers:

5G Wafer Test and the New Age of Parallelism
Monday | June 3 | 8:30 – 9:00AM

Probing 5G Devices Like It’s No Big Deal
Monday ӏ June 3 ӏ 2:00 – 2:30PM

Hybrid MEMS Probe Technology 2.0
Monday | June 3 | 3:00 – 3:30pm

A Fully Automatic Electro-Optical Test System Enabling the Development of a Silicon Photonic Technology Platform
Monday | June 3 | 4:00 – 4:30

Silicon Photonics – Challenges and Solutions for Wafer-Level Production Tests
Monday | June 3 | 4:30 – 5:00

Terminated Tester Resource Enhancement (TTRE) Improves Signal Integrity Performance at higher signal sharing enables wafer sort at higher frequency and higher parallelism
Tuesday | June 4 | 11:00 – 11:30

High Density Probe Card PCB’s, are you being your own worst enemy to achieving Higher Parallelism on your Designs?
Tuesday | June 4 | 2:00 – 2:30

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The full agenda can be found here. Be sure to swing by and visit with us. We’ll be in booth #9 this year in the exhibition hall and the hours are 5:00 – 8:00 on Monday at 2:30 – 5:00 on Tuesday.

See you soon!